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ADE7518
TIMERS
The ADE7518 has three 16-bit timer/counters: Timer/Counter 0,
Timer/Counter 1, and Timer/Counter 2. The timer/counter
hardware is included on chip to relieve the processor core of
overhead inherent in implementing timer/counter functionality in
software. Each timer/counter consists of two 8-bit registers: THx
and TLx (x = 0, 1, or 2). All three timers can be configured to
operate as timers or as event counters.
When functioning as a timer, the TLx register is incremented
every machine cycle. Thus, users can think of it as counting
machine cycles. Because a machine cycle on a single cycle core
consists of one core clock period, the maximum count rate is
the core clock frequency.
Table 91. Timer SFRs
When functioning as a counter, the TLx register is incremented
by a 1-to-0 transition at its corresponding external input pin:
T0, T1, or T2. When the samples show a high in one cycle and a
low in the next cycle, the count is incremented. Because it takes
two machine cycles (two core clock periods) to recognize a 1-to-0
transition, the maximum count rate is half the core clock frequency.
There are no restrictions on the duty cycle of the external input
signal, but to ensure that a given level is sampled at least once
before it changes, it must be held for a minimum of one full
machine cycle. User configuration and control of all timer
operating modes is achieved via the SFRs listed in Table 91.
SFR
TCON
TMOD
TL0
TL1
TH0
TH1
T2CON
RCAP2L
RCAP2H
TL2
TH2
Address
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0xC8
0xCA
0xCB
0xCC
0xCD
Bit Addressable
Yes
No
No
No
No
No
Yes
No
No
No
No
Description
Timer/Counter 0 and Timer/Counter 1 Control (see Table 93).
Timer/Counter 0 and Timer/Counter 1 Mode (see Table 92).
Timer 0 Low Byte (see Table 96).
Timer 1 Low Byte (see Table 98).
Timer 0 High Byte (see Table 95).
Timer 1 High Byte (see Table 97).
Timer/Counter 2 Control (see Table 94).
Timer 2 Reload/Capture Low Byte (see Table 102).
Timer 2 Reload/Capture High Byte (see Table 101).
Timer 2 Low Byte (see Table 100).
Timer 2 High Byte (see Table 99).
TIMER REGISTERS
Table 92. Timer/Counter 0 an d Timer/Counter 1 Mode SFR (TMOD, 0x89)
Bit
7
Mnemonic
Gate1
Default
0
Description
Timer 1 Gating Control. Set by software to enable Timer/Counter 1 only when the INT1 pin is high and the
TR1 control is set. Cleared by software to enable Timer 1 whenever the TR1 control bit is set.
6
C/T1
0
Timer 1 Timer or Counter Select Bit. Set by software to select counter operation (input from the T1 pin).
Cleared by software to select the timer operation (input from the internal system clock).
5 to 4
T1/M1,
T1/M0
00
Timer 1 Mode Select Bits.
T1/M[1:0] Result
00 TH1 operates as an 8-bit timer/counter. TL1 serves as a 5-bit prescaler.
01 16-Bit Timer/Counter. TH1 and TL1 are cascaded; there is no prescaler.
10 8-Bit Autoreload Timer/Counter. TH1 holds a value to reload into TL1 each time it overflows.
11 Timer/Counter 1 stopped.
3
Gate0
0
Timer 0 Gating Control. Set by software to enable Timer/Counter 0 only when the INT0 pin is high and the
TR0 control bit is set. Cleared by software to enable Timer 0 whenever the TR0 control bit is set.
2
C/T0
0
Timer 0 Timer or Counter Select Bit. Set by software to the select counter operation (input from the T0 pin).
Cleared by software to the select timer operation (input from the internal system clock).
1 to 0
T0/M1,
T0/M0
00
Timer 0 Mode Select Bits.
T0/M[1:0] Result
00 TH0 operates as an 8-bit timer/counter. TL0 serves as a 5-bit prescaler.
01 16-Bit Timer/Counter. TH0 and TL0 are cascaded; there is no prescaler.
10 8-Bit Autoreload Timer/Counter. TH0 holds a value to reload into TL0 each time it overflows.
11
TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits. TH0 is an
8-bit timer only, controlled by Timer 1 control bits.
Rev. 0 | Page 93 of 128
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